As PDPs, surface discharge AC-type PDPs with three electrodes have been widely known. These PDPs have a number of surface dischargeable display electrodes arranged in a horizontal direction on an inner surface of a front side (display surface side) substrate and a number of selective electrodes (also referred to as address electrodes or data electrodes) arranged in a perpendicular direction on an inner surface of a rear side substrate. The front- and rear-side substrates are disposed to face each other and the periphery of the substrates is sealed to form a discharge space inside. Portions where the display electrodes and the address electrodes intersect each other serve as cells.
The display electrodes are constituted of Y electrodes used for selecting a cell to be lit and X electrodes for applying the same voltage to all cells. The Y electrodes and X electrodes are alternately arranged.
In the PDPs of this structure, a driving method generally called an address/display separation method is employed for gradation display. In other words, one frame is divided into a plurality of subfields to which weights are assigned. Each subfield includes an address period for selecting a cell to be lit and a sustain period for causing the selected cell to emit light.
For display, while the Y electrodes are used as scan electrodes to scan a screen, a voltage (generally referred to as an address voltage) is applied to a desired address electrode to generate an address discharge between the Y electrode and the address electrode so that charges are formed in a cell to be lit. Then, voltages for display (generally referred to as sustain voltages) are alternately applied to the X and Y electrodes to repeat sustain discharges between the X and Y electrodes for the number of times corresponding to the weight assigned to a subfield.
As a waveform of voltages applied at the sustain discharge, such rectangular waves as shown in FIG. 27 are usually employed, and a method of alternately applying the rectangular waves is common. As a modified example of such rectangular waves, an offset waveform shown in FIG. 28 may be used in order to increase the driving margin or improve the light emission efficiency.
The offset waveform is a voltage waveform in which an offset voltage is superposed on a rectangular wave, and is known from the disclosure of, for example, Japanese Unexamined Patent Publication No. SHO 52-150941, Japanese Unexamined Patent Publication No. SHO 52-150940, Japanese Unexamined Patent Publication No. SHO 50-39024, Japanese Unexamined Patent Publication No. HEI 3-259183 and Japanese Unexamined Patent Publication No. HEI 4-267293.
Furthermore, a circuit for forming such an offset waveform is disclosed in Japanese Unexamined Patent Publication No. 2001-13919. The circuit disclosed in this publication is as shown in FIG. 29. The circuit for forming an offset waveform will be described below.
In the circuit of FIG. 29, a condenser C signifies a panel capacity of a PDP. A resistance R is a line resistance, and an inductor L1 together with the condenser C forms a resonance circuit. A source of voltage Vo applies an offset voltage, and a source of voltage Vs applies a rectangular wave. Switches SW1 and SW2 control application timing of voltages Vo and Vs, respectively.
FIG. 30 is a timing diagram of switches SW1 and SW2. In the figure, t1 indicates a time when a wave starts to rise, t2 indicates a time when the maximum voltage is reached, and t3 indicates a time when the voltage is at Vs.
The maximum light emission efficiency can be obtained on the condition that a discharge starts when the voltage is at the maximum, and where tf is a discharge start time, the optimum value can only be obtained at a moment when tf=t2.
Exemplary diagrams in which the discharge start time does not match the optimum value are shown in FIGS. 31 and 32.
FIG. 31 is a timing diagram when tf>t3. In this diagram, since a discharge starts at a voltage Vs, the light emission efficiency is equivalent to that when an offset waveform is not applied and a usual rectangular wave is applied. Furthermore, the light emission efficiency is lower than that when tf=t2.
FIG. 32 is a timing diagram when tf<t3. In this diagram, since a discharge starts in the middle of wave rise, a discharge takes place without a sufficient voltage being applied due to a voltage drop associated with the discharge. For this reason, the light emission efficiency is lower than that when tf=t2.
The maximum light emission efficiency is achieved when tf=t2. Where t2>tf>t3, the light emission efficiency decreases as the discharge start time tf becomes late.
As described above, in plasma display using an offset voltage, there is an optimum range for the relationship between application timing of the offset waveform and discharge start time, and if the relationship is not in an appropriate range, the light emission efficiency decreases.
With respect to the relationship between offset waveform application timing and discharge start time, conventional circuits have a problem that rise timing and fall timing of the offset waveform depend on the time constant of LC resonance, and thereby the adjustment of timings is difficult. Since the discharge start time tf changes in accordance with the amount of priming particles which varies with a display state, display panels operate unstably with conventional circuits.
The present invention has been made in view of such circumstances and an object thereof is to improve the light emission efficiency of a plasma display panel by adding a mechanism of freely adjusting rise timing and fall timing of an offset voltage waveform in accordance with discharge timing.